One important processor model is that of vector processing. This model has been used in prior art super computers for many years. Typical features of this model are the use of specialized vector instructions, specialized vector hardware, and the ability to efficiently operate on blocks of data. It is this very ability to operate typically only on vector data types that makes the model inflexible and unable to efficiently handle diverse processing requirements. In addition, in prior art vector processors, support for control scalar processing was typically done in separate hardware or in a separate control processor. Another processor model is the prior art very long instruction word (VLIW) processor model which represents a parallel processing model based on the concatenation of standard uniprocessor type single function operations into a long instruction word with no specialized multicycle vector processing facilities. To efficiently operate a block-data vector pipeline, it is important to have an efficient interface to deliver the individual vector elements. For this purpose, a successful class of prior art vector machines have been register based. The register based vector processors provide high performance registers for the vector elements allowing efficient access of the elements by the functional execution units. A single vector instruction tied to an implementation specific vector length value causes a block data multicycle operation. In addition, many vector machines have provided a chaining facility where operations on the individual vector elements are directly routed to other vector functional units to improve performance. These previous features and capabilities provide the background for the present invention. It is an object of the present invention to incorporate scalar, VLIW, and flexible vector processing capabilities efficiently in an indirect VLIW processor.
In typical reduced instruction set computer (RISC) and VLIW processors, the access of register operands is determined from short instruction word (SIW) bit-fields that represent the register address of operands stored in a register file. In register-based vector processors, specialized hardware is used. This hardware is initiated by a single vector instruction and automates the accessing of vector elements (operand data) from the dedicated vector registers. The multicycle execution on the block of data is also automated.
In the prior art, there have also been specialized hardware techniques used to support the automatic accessing or register operand data. For example, U.S. Pat. No. 5,680,600 which describes a technique for accessing a register file using a loop or repeat instruction to automate the register file addressing. This approach ties the register addressing to a loop or repeat instruction which causes a load or store instruction to be repeated while directing the register address to increment through a register file's address space. An electronic circuit is specified for reducing controller memory requirements for multiple sequential instructions. Thus, this prior art approach appears to be applied only to load and store type operations invoked by a special loop or repeat instruction. As such, it is not readily applicable to indirect VLIW ManArray processors as addressed further below.